1. Technical Field
The present invention relates generally to a power amplifier, and, more particularly, to an envelope tracking power amplifier
2. Description of the Related Art
Recent wireless communication systems utilize a modulation method having a high peak to average power ratio (PAPR), such as orthogonal frequency division multiplexing (OFDM), in order to process a large amount of data while efficiently utilizing limited frequency resources.
In a modulation method having a high PAPR, a high-efficiency power amplifier, such as a class C, D, E or F power amplifier, may be used as a power amplifier (PA) in order to maximize efficiency. Although these power amplifiers can operate with high efficiency in a compression region, i.e., in a saturation region, they require an additional linearization technique due to the non-linearity of the compression region and do not significantly improve efficiency in terms of an overall system.
Furthermore, these power amplifiers operate with high efficiency in the saturation region, but have poor efficiency in a back-off region lower than a maximum power point. Wireless communication systems operate in the back-off region lower than the PAPR during most of their operating time, thus resulting in poor efficiency in average power.
In order to solve these problems, there have been proposed an envelope tracking (ET) power amplification method of applying a bias, having a voltage level modulated in response to the envelope of an RF input signal, and the RF input signal to a linear mode power amplifier, rather than applying a fixed bias to the linear mode power amplifier, and an envelope elimination and restoration (EER) power amplification method of applying an input signal, including only a phase component left by removing an envelope using a bias, modulated according to the envelope, and a limiter, to a switching mode power amplifier.
Although the ET power amplification method has slightly lower efficiency than the EER power amplification method, it is advantageous in that a reduction in linearity is smaller despite timing mismatch that is inevitable between the RF input signal path of the power amplifier and the path of a modulated bias path and also in that the structure of the bias modulator is simpler.
Moreover, through the combination of the EER power amplification method and the ET power amplification method, there has been proposed hybrid ET power amplification method of applying a bias, having a voltage level modulated in response to an envelope, and an RF input signal to a switching mode power amplifier.
In the hybrid ET power amplification method, a bias modulator can achieve a high-speed operation and high efficiency using a linear amplifier providing a wide bandwidth and a switching amplifier having high efficiency in order to generate a modulated bias voltage based on a detected envelope.
In general, the overall efficiency of the bias modulator is determined based on bias voltage, output to the power amplifier, and load resistance because it increases or decreases in proportion to output power. In other words, when an output bias voltage modulated by the bias modulator is low because the size of an envelope is small, the power efficiency of the bias modulator is also low.
In order to overcome this problem, a DC-DC converter is added. When an output bias voltage is low, an operating voltage for the linear amplifier is lowered using the DC-DC converter, thereby being able to improve the efficiency of the bias modulator. However, this method is problematic in that the linear amplifier should be designed to operate desirably at all different operating voltages and both a circuit size and power consumption are increased due to the added DC-DC converter.
As a result, there is a need for a method for improving the efficiency of a bias modulator in a wide power region without additionally using analog circuits that require a relatively large area.